Research Engineer, Chip Design RL
Anthropic · San Francisco, CA · AI Research & Engineering · listed October 21, 2026
The shape of it
Seniority
Not stated
Where
Hybrid
Stated pay
$500,000 – $850,000 USD
Requirements listed
3
Length
1,025 words
In the posting’s own words
We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.
What it asks for · 3
- Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
- Experience with reinforcement learning, evaluations or environments.
- Familiarity with high-level synthesis or architecture simulators.
Tools and skills named
Models & research
- Evaluations2×
- Machine learning
- Reinforcement learning
Operations & finance
- Excel
Product & design
- Roadmap
Words the posting leans on
- design10×
- optimization3×
- research3×
- chip design2×
- engineer2×
- evaluations2×
- experience2×
- expertise2×
- formal2×
- hardware2×
- models2×
- physical design2×
- rtl2×
- silicon2×
- synthesis2×
- verification2×
Counted from the posting after the mission statement and the legal notices are set aside. The ones near the top are the ones a screener is looking for.
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